Чтобы сбалансировать разговор про cache-ы приведу цитату про MF (EC12 CPU) cache:flip_flop wrote:...
http://en.wikipedia.org/wiki/Smart_Cache
В процессоре это L3 cache. Те же 2.5 MB/core для 18-ти ядерного E5-2699 v3: 18*2.5=45 MB
Each core has its own 160-KB cache Level 1 (L1), split into 96 KB for data (D-cache) and 64
KB for instructions (I-cache). The L1 cache is designed as a store-through cache, meaning
that altered data is also stored to the next level of memory.
The next level is the private cache Level 2 (L2) on each core. This cache has 2 MB, split into
1 MB D-cache and 1 MB I-cache, and also designed as a store-through cache.
The cache Level 3 (L3) is also on the PU chip. It is shared by the six cores, has 48 MB, and is
designed as a store-in cache.
Cache levels L2 and L3 are implemented on the PU chip to reduce the latency between the
processor and the large shared cache L4, which is on the two SC chips. Each SC chip has
192 MB, resulting in 384 MB of L4 cache, which is shared by all PUs on the MCM. The L4
cache uses a store-in design.
Я сложил все эти cache-ы, получилось примерно 61 MB на 6 cores PU. Плюс, стандартно, 384 MB на 6 PUs (36 cores) L4 cache на MCM (Multiple Chip Modume).
P.S. И все это на 5.5 GHz работает.
