zVlad wrote:dB13 wrote:zVlad wrote: Вот простой вопрос. Что есть у Интел "вместо" МФ-кого компоратора?
High Precision Event Timers
http://www.intel.com/hardwaredesign/hpetspec_1.pdf
.....
Минуточку, не надо меня разводить. Я спрашивал не вообще о таймер производимых фирмой Интел, я спрашивал о таймерах имеющихся в процессоре x86.
Какая разводка, "У меня все ходы записаны!"
В самом процессоре:
Local APIC Timer
The local APIC unit contains a 32-bit programmable timer that is available to software to time
events or operations. This timer is set up by programming four registers: the divide configuration
register (see Figure 8-10), the initial-count and current-count registers (see Figure 8-11),
and the LVT timer register (see Figure 8-8).
The time base for the timer is derived from the processor’s bus clock, divided by the value specified
in the divide configuration register.
The timer can be configured through the timer LVT entry for one-shot or periodic operation. In
one-shot mode, the timer is started by programming its initial-count register. The initial count
value is then copied into the current-count register and count-down begins. After the timer
reaches zero, an timer interrupt is generated and the timer remains at its 0 value until reprogrammed.
In periodic mode, the current-count register is automatically reloaded from the initial-count
register when the count reaches 0 and a timer interrupt is generated, and the count-down is
repeated. If during the count-down process the initial-count register is set, counting will restart,
using the new initial-count value. The initial-count register is a read-write register; the currentcount
register is read only.
The LVT timer register determines the vector number that is delivered to the processor with the
timer interrupt that is generated when the timer count reaches zero. The mask flag in the LVT
timer register can be used to mask the timer interrupt.
TSC:
The time-stamp counter is a model-specific 64-bit counter that is reset to zero each time the
processor is reset. If not reset, the counter will increment ~9.5 x 10^16 times per year when
the processor is operating at a clock rate of 3GHz. At this clock frequency, it would take
over 190 years for the counter to wrap around. The RDTSC instruction loads the current
count of the time-stamp counter into the EDX:EAX registers.
но опять же я не вижу никакой необходимости притягивать необходимость виртуализации к обеспечению разделения доступа. reference monitor - и все дела.